Computer Science and Engineering

CSE125L Logic Design with Verilog Laboratory

Laboratory sequence illustrating topics covered in course 125. Two 2-hour laboratory sessions per week. Students are billed a materials fee. (Formerly Computer Engineering 125L.)

Requirements

Prerequisite(s): CSE 100 and CSE 100L. Concurrent enrollment in CSE 125 is required.

Credits

2

Quarter offered

Spring

Instructor

Jose Renau Ardevol, Matthew Guthaus, Heiner Litz